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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
www.ti.com
Table 5-15. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory (1) (2)
Figure 5-21 ) (4)
CV DD = 1.05 V
(3)
(see Figure 5-19 and
NO.
PARAMETER
MIN
DV DDEMIF = 3.3/2.75/2.5/1.8 V
NOM
MAX
UNIT
READS and WRITES
1
t d(TURNAROUND)
Turn around time
(TA)*E - 13
(TA)*E
(TA)*E + 13
ns
READS
3
4
5
6
7
8
9
10
11
t c(EMRCYCLE)
t su(EMCEL-EMOEL)
t h(EMOEH-EMCEH)
t su(EMBAV-EMOEL)
t h(EMOEH-EMBAIV)
t su(EMBAV-EMOEL)
t h(EMOEH-EMAIV)
t w(EMOEL)
t d(EMWAITH-EMOEH)
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 1)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_OE low
Output hold time, EM_OE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_OE low
Output hold time, EM_OE high to EM_A[20:0] invalid
EM_OE active low width (EW = 0)
EM_OE active low width (EW = 1)
Delay time from EM_WAITx deasserted to EM_OE high
(RS+RST+RH)*E - 13
(RS+RST+RH+(EWC*16))*E - 13
(RS)*E-13
-13
(RH)*E - 13
-13
(RS)*E-13
(RH)*E-13
(RS)*E-13
(RH)*E-13
(RST)*E-13
(RST+(EWC*16))*E-13
4E-13
(RS+RST+RH)*E
(RS+RST+RH+(EWC*16))*E
(RS)*E
0
(RH)*E
0
(RS)*E
(RH)*E
(RS)*E
(RH)*E
(RST)*E
(RST+(EWC*16))*E
4E
(RS+RST+RH)*E + 13
(RS+RST+RH+(EWC*16))*E +139
(RS)*E+13
+13
(RH)*E + 13
+13
(RS)*E+13
(RH)*E+13
(RS)*E+13
(RH)*E+13
(RST)*E+13
(RST+(EWC*16))*E+13
4E+13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITES
EMIF write cycle time (EW = 0)
(WS+WST+WH)*E-13
(WS+WST+WH)*E
(WS+WST+WH)*E+13
ns
15
16
17
18
19
20
21
t c(EMWCYCLE)
t su(EMCSL-EMWEL)
t h(EMWEH-EMCSH)
t su(EMBAV-EMWEL)
t h(EMWEH-EMBAIV)
t su(EMAV-EMWEL)
t h(EMWEH-EMAIV)
EMIF write cycle time (EW = 1)
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 1)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_WE low
Output hold time, EM_WE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_WE low
Output hold time, EM_WE high to EM_A[20:0] invalid
(WS+WST+WH+(EWC*16))*E - 13
(WS)*E - 13
-13
(WH)*E-13
-13
(WS)*E-13
(WH)*E-13
(WS)*E-13
(WH)*E-13
(WS+WST+WH+(EWC*16))*E
(WS)*E
0
(WH)*E
0
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS+WST+WH+(EWC*16))*E +
13
(WS)*E + 13
+13
(WH)*E+13
+13
(WS)*E+13
(WH)*E+13
(WS)*E+13
(WH)*E+13
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
(2)
(3)
(4)
Timing parameters are obtained with 10pF loading on the EMIF pins.
TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These
parameters are programmed via the Asynchronous Configuration and Asynchronous Wait Cycle Configuration Registers.
E = SYSCLK period in ns. For example, when SYSCLK is set to 100/120 MHz, E = 10/8.33 ns, respectively.
EWC = external wait cycles determined by EM_WAITx input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified
by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
94
Peripheral Information and Electrical Specifications
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